In a variety of instrumentation applications, including acoustics technology and general audio frequency signal processing, it is necessary to delay wideband analog information without introducing excessive distortion of the signal waveform. Typically, the longer the delay needed the higher becomes the complexity and cost of the network used to produce the delay.
One approach commonly used for obtaining short duration delays involves the employment of lumped or distributed constant fixed delay lines. Such lines are generally only practically useful for producing delays of the order of a few microseconds. When very long delays are attempted with such lines, the signal waveform tends to become unacceptably distorted.
A well-known complex and costly electronic approach to obtaining longer delays involves the use of analog to digital converters to sample and digitize the analog information. Digital serial shift registers are then employed to delay the digital samples, and finally a digital to analog converter is used to reconstruct an acceptable delayed version of the original analog signal. The cost of the digital equipment necessary for this approach can be prohibitive in many applications.
Another known method for signal delaying used commonly in the broadcast and recording industry involves the use of electromechanical delay techniques. However, the mechanical size and weight of the devices employed do not lend themselves to being useful in many critical instrumentation application.
In recent years an electronic element known as a charge coupled device (CCD) has been developed. These CCD devices are comprised of a plurality of series connected charge storage cells. The device functions in the discrete-time domain by storing samples of an input signal as packets of charge in an analog memory. The samples of charge are then transferred from stage to stage across the chip under the control of a sequence of clock pulses. The charge carrier movement is due to voltage differences between adjacent charge storing wells that serially transfer or couple the charge in one cell to an adjacent cell. In physical terms, a piece of crystalline solution coated with a thin insulating layer of S.sub.i O.sub.2 forms the CCD; and on top of the insulation layer a series of gates are deposited. The silicon and gate layer form two conductive elements separated by the S.sub.i O.sub.2 insulating layer. The charge in this capacitor-like structure is contained in a charge well that forms underneath the electrode in the silicon. By applying suitably timed clock pulses to the overlying clock lines on the CCD structure, sampled information (in the form of stored charge packets) is caused to be serially shifted along from cell to cell. The delay which a given charge packet experiences before being shifted to the next cell is determined by the frequency of the above-mentioned clock pulses. A CCD is capable of performing both the functions of sampling and delaying with a minimum of ancillary circuitry, thus making it a practical and cost effective alternative for use in many instrumentation applications. CCD's have the advantage of very low power consumption, high speed, small size and weight, and high density of charge storing elements. Suitable electronic ancillary components are commercially available so that hybrid electronic test packages employing the CCD's can be constructed in a manner such that the packages have relatively small size and weight.
In order to employ the CCD as a signal sampling and delaying means, it is necessary (according to the well-known Sampling Theorem) that the signal be sampled at a rate corresponding to at least twice the frequency of its highest significant frequency component. Thus, by directly using a CCD (or a series connection of CCD's) for sampling and delaying application, the delay attainable by a charge packet stored in a given cell is limited by the frequency content of the signal being sampled. Therefore, for a broad bandwidth signal to be sampled, it may be necessary to cascade several charge coupled devices together in order to obtain the desired delay. This dependence of the storage cell delay time upon the bandwidth of the analog signal being sampled is undesirable since it severely limits the design flexibility of such systems.
Consider for example the problem of delaying a band limited signal such as that shown in FIG. 1 for a time interval of .tau.=40 ms. If the highest significant frequency component of the band limited signal is f.sub.c =20 KHz, then it would be necessary to sample this signal at a rate of at least 40 KHz. Using typical off-the-shelf CCD devices having independent sections of 512 serially connected charge coupled cells, a minimum of 1600 cells would be required to attain the desired delay. Thus four serially connected sections using a sampling rate of 51.2 KHz would be necessary in a practical realization. Such extensive cascading of charge coupled devices is not desirable since appreciable difficulty is then experienced in adjusting the bias and gain levels of the devices and serious distortions due to charge transfer inefficiency tend to occur. Thus it is seen that the prior art practice of using cascaded charge coupled devices and employing a charge cell delay time which is determined by the bandwidth of the analog signal being delayed (as depicted in FIGS. 3 & 4) is not an altogether satisfactory approach.
It is therefore an object of the instant invention to provide a circuit arrangement having more versatility, more design flexibility, and resulting in a decreased distortion level of the analog signal being delayed.